Huawei’s Quad-Chiplet AI Chip Could Challenge NVIDIA and TSMC
Huawei has recently filed a patent for a quad-chiplet design , believed to be intended for its upcoming AI accelerator, the Ascend 910D . The design closely resembles NVIDIA’s approach with the quad-chiplet Rubin Ultra GPU , but what makes this patent even more intriguing is the mention of Huawei’s efforts in advanced chip packaging technology.
According to the document, Huawei appears to be developing packaging methods that could potentially compete with TSMC’s cutting-edge solutions — a major step forward that might help the company bypass U.S. export restrictions and close the performance gap with NVIDIA’s top-tier AI GPUs at a faster pace.
While the patent doesn’t explicitly name the Ascend 910D, there’s enough detail to reasonably suggest it’s connected. Industry insiders have already been hinting at the possibility of a next-gen quad-chiplet version of the Ascend 910 series, making this patent all the more significant.
One particularly interesting technical detail involves how the chiplets are interconnected. Instead of relying on traditional interposers, the patent suggests a bridge-like structure — similar to TSMC’s CoWoS-L or Intel’s EMIB combined with Foveros 3D . This could offer better performance and efficiency compared to standard packaging techniques.
Additionally, since this processor is expected to be aimed at AI training workloads , it would likely come paired with high-bandwidth memory modules like HBM , which may also use interposer-level integration for improved data throughput.
While Huawei and SMIC may still lag behind global leaders like TSMC in advanced lithography, they appear to be making significant progress in chip packaging technology . If true, this could give Chinese tech firms a powerful workaround to U.S. export restrictions that limit access to cutting-edge chip manufacturing tools.
The idea is simple: instead of relying on the latest process nodes, companies can use advanced packaging techniques to combine multiple older-generation chiplets into a single, high-performance unit — potentially matching or closely approaching the performance of chips built on leading-edge nodes.
Now, let’s dive into some speculative math (and we’ll note where things get uncertain). The original Ascend 910B is believed to have a die size of around 665 mm² . If the upcoming Ascend 910D uses four such chiplets, the total logic area alone would jump to approximately 2,660 mm² .
Each Ascend 910B also integrates four HBM chiplets , which we’ll estimate at 85 mm² each . So with four chiplets per GPU, the 910D would pack 16 HBM modules , bringing the total memory footprint to roughly 1,366 mm² .
Putting it all together — logic + memory — we’re looking at a total silicon area of about 4,020 mm² . By TSMC’s standards, this falls into the category of a five-reticle design (with one EUV reticle covering around 858 mm²), a level of complexity that TSMC itself isn’t expected to bring to mass production until 2026 .
Back in April, when the first rumors about Huawei’s quad-chiplet Ascend 910D emerged, we took them with more than just a grain of salt. But now, the story seems to be gaining real momentum. Reports indicate that Huawei is indeed developing a four-die AI accelerator under the name Ascend 910D , and early projections suggest it could potentially outperform NVIDIA’s H100 GPU in per-package performance.
Still, it’s important to remain cautious — not every patent leads to an actual product, and not every rumor turns into reality. But if Huawei really is heading in this direction, it could mark a major shift in the global AI chip race.